My first mini-computer was a PDP-8/L I came across in the final hours of my first Dayton Hamvention. I was fascinated by the switches and lights and the scores of internal cards, and since up to that point, I’d only had experience with 8-bit 1802 and 6502 microcomputers, I marvelled at how this larger machine did its job with no chip larger than 16 pins. I didn’t know it at the time, but the PDP-8/L was an excellent choice for learning about machine internals. Originally released in 1968 with its brother the PDP-8/i, it was an early TTL machine, made up largely of 7400-series logic (predecessor machines had a similar architecture, but were composed of discrete transistor logic, no chips in the CPU and few RTL chips in the periperals). For machines of this era, DEC manufactured dozens of general-purpose and specialty-purpose “M-Series” modules. They color-coded the handles of their logic cards – Green for power, amplifier, and general-purpose analog boards, Maroon for TTL logic, White for input and output cable boards, Amber for analog I/O, along with the older Red and Blue and Black transistor and relay boards. The PDP-8/L is made up of a processor section of Maroon-handled boards, core memory and its Green-handled amplifiers and such, and a final section in the back of Maroon-handled I/O boards. In that back I/O section, there are a few slots specially wired for two specific in-cabinet I/O options – the 110 bps console teletype option, and the PR8L “High-speed Paper Tape” option.
A standard PDP-8/L came with the CPU fully populated, an optional parity-memory circuit, 4Kwords of internal core, and the console TTY interface, all for about $10,000, not including the ASR-33 teletype. Typical operation revolved around reading pre-punched paper tapes (copied from friends or from the DECUS library or purchased from Digital) with assemblers and compilers, or even a rudimentary interactive language called FOCAL (FOrmula CALculator). The TTY was used to read programs, save programs and interact via the keyboard and printer. While versatile, it was slow. The mechanical nature of the TTY limited the speed to 10 characters per second. That wasn’t so bad for typing, but loading a 3K program into memory took over 20 minutes. One solution was an optical (not mechanical) papertape reader, and a high-speed (50 characters per second) punch. As packaged to work with the PDP-8/L, it was called the PR8L (Punch-Reader for 8/L).
The PR8L consisted of the punch and reader mechanism itself, a rack-mount box about 1/3 the volume of the PDP-8/L, and the three cards necessary to add the I/O instructions to the PDP-8’s instruction set to operate the mechanism. I’ve had a PR8L for many years (it was a great upgrade to my original machine), and recently, a friend has been reverse-engineering most of the M-series logic cards and put out the call for photographs of various versions of the cards so he could document the differences. We’ve collaborated before on projects for these grand old beasts, so I was happy to help his latest endeavor.
The M705 is the Reader Control board. Using just under 40 NAND gates and just over a dozen D flip-flops, it takes the data from the reader phototransistors and gates it onto the PDP-8 data bus when the right IOT instructions are being executed (unlike most modern processors, the PDP-8 does not use memory-mapped I/O; instructions of the form 6NNX are special I/O instructions – NN is the I/O device number (01 for this board, 02 for the M710), and X is the function to perform)
The M710 is the Punch Control board. It uses 14 NANDs, a dozen inverters, a dozen D flip-flops and three “one-shot” delays to grab a byte from the data bus and send it to the punch relay drivers at exactly the right time to get the mechanical parts of the punch to make the right holes at the right place on the blank paper tape.
The M715 is the Reader Clock board. With 10 NAND gates, 2 NOR gates, half-a-dozen inverters, three “one-shot” delays and a handful of transistors and passives, the M715 generates three 150ns clock pulses to synchronize the reader timing.
Less than 10 years later, VLSI chips like the 6820, 6821, 6522, and such, would provide multiple 8-bit I/O interfaces with handshaking, interrupt generation and more. In 1968, however, these functions were built up one NAND gate and one flip-flop at a time. They took up more space, but were easy to debug and inexpensive to repair.